ALU design by VHDL using FPGA technology and micro learning in engineering education
Yazarlar (2)
Ismail Said
Prof. Dr. Muhammet Serdar ÇAVUŞ Kastamonu Üniversitesi, Türkiye
| Makale Türü | Özgün Makale (Uluslararası alan indekslerindeki dergilerde yayınlanan tam makale) | ||
| Dergi Adı | British Journal of Computer, Networking and Information Technology, January | ||
| Makale Dili | – | Basım Tarihi | 01-2018 |
| Cilt / Sayı / Sayfa | 0 / 0 / 1–18 | DOI | – |
| Makale Linki | https://www.researchgate.net/profile/M-Serdar-Cavus/publication/329360355_ALU_DESIGN_BY_VHDL_USING_FPGA_TECHNOLOGY_AND_MICRO_LEARNING_IN_ENGINEERING_EDUCATION/links/5c04347392851c63cab5cda5/ALU-Design-by-VHDL-Using-FPGA-Technology-and-Micro-Learning- | ||
| UAK Araştırma Alanları |
Atom, Molekül ve Lazer Fiziği
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| Özet |
| The aim of this study is to develop case-study called Allowing Complexity to Complex Project (ACCP) for micro-learning in order to achieve high performance in computer architecture education and to test the legitimacy of classical teaching methods. The Arithmetic/Logic Unit (ALU) design was used as an example of the ACCP which consists of many examples and models aimed at developing students' skills in using complex arithmetic logical shifting and rotation instructions. Moreover, in this study, a real-world project on Field Programmable Gate Arrays (FPGA) devices was also developed using micro learning (ML). To this end, various hardware and software programs designed for computer architecture education and training were combined with improved instructional and attractive examples. |
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